The present invention relates to improved power leakage control in very large scale integrated (VLSI) circuits, and more particularly relates to a design structure for fabricating a scan-based VLSI circuit with improved input vector control (IVC), by use of scan-chain logic to set sleep mode and reset flip flops comprising the scan-chain logic from a low-power state with the same logical values that the flip-flops were set to at initialization.
This and related power leakage problems in VLSI processors are discussed in detail in a paper by Rohrer, et al., POWERPC 970 IN 130 NM AND 90 NM TECHNOLOGY, Pages 68-69, ISSCS 2004. Power leakage reduction in VLSI processors is not just an issue for operation and performance, but in manufacturing as well. For example, DAC's publication FUTURE PERFORMANCE CHALLENGES IN NANOMETER DESIGN, pages 3-8, DAC 2001, reports that a reduction of 10 W in the power consumption of the Intel Pentium microprocessor is known to realize a decrease in packaging cost by more than three. For that matter, leakage power consumption for normal operation causes a secondary power consumption in energy to cool the IC as a consequence. If not cooled, increased temperature conditions can degrade IC performance and reliability.
Consequently, various processes and techniques have developed for reducing power dissipation, whether by attempting to reduce static leakage current or prevent unnecessary switching, to name two. For example, in a paper by Abdollahi, et al., LEAKAGE CURRENT REDUCTION IN CMOS VLSI CIRCUITS BY INPUT VECTOR CONTROL (IVC), vol. 12, IEEE Trans. On VLSI Systems (No. 2, February 2004), the authors provide some promising insight on power reduction using input vector control (IVC) processes and suggested improvements. IVC techniques introduce sleep transistors into the VLSI design to mitigate increased leakage current. Other work concerning IVC designs includes Rao, et al., A HEURISTIC TO DETERMINE LOW LEAKAGE SLEEP STATE VECTORS FOR CMOS COMBINATIONAL CIRCUITS, pages 689-692, ICCAD 2003, and Chopra, et al., IMPLICIT PSEUDO BOOLEAN ENUMERATION ALGORITHMS FOR INPUT VECTOR CONTROL, pages 767-772, DAC 2004 (Jun. 7-11, 2004). The cited references appear to agree that leakage power consumption within an IC device depends strongly on the state of the IC device input and of the internal memory elements (e.g. latches), which affects switching and leakage significantly.
Input Vector Control (IVC) techniques exploit the property that controlling input state can reduce chip-wide power consumption, as discussed in the referenced papers, and in U.S. Pat. No. 7,100,144 to Jacobson et al., commonly owned and incorporated by reference herein. In scan-based VLSI designs, flip-flops are connected to enable two modes of operation: normal mode and test mode. The inputs are multiplexed to operate both modes separately. During test, a test vector is applied in scan mode; the sequential or combinatorial logical circuit state outputs are captured in the flip-flops as configured in normal operational mode. This operation is modified to place the same logical circuits in stand-by or sleep mode. That is, during sleep mode, the device inputs are forced to a state in which power consumption due to leakage is minimal using the IVC concept. Abdollahi asserts that attainable static power reductions that approach 25% are readily achievable using their method, which is substantial.
The processes discussed by Abdollahi and Chopra include inserting a multiplexer at particular nodes in IC designs and using IVC to stimulate the combinational logic to the desired low leakage state. The multiplexer is controlled with a sleep signal for compelling the gates to their low-leakage state. During normal operational mode, the multiplexer selects the original signal directed as the circuit input, and passes it to the logic gate(s). When in sleep mode, a signal that defines a low-leakage output state (derived from the IVC vector) is provided to the logical gate input. Abdollahi proposes refining the process by reducing the multiplexer to simpler gates. The Abdollahi approach, however, has its drawbacks. For example, the suggested approach introduces additional logic in the critical circuit or logic paths, which degrades or slows timing. In addition, Abdollahi's approach requires a global sleep signal with a very large fan-in/fan-out. This results in a large routing overhead in the original circuit floorplan, where the fan-out tree itself consumes significant static and dynamic power each time the additional logic path sets and resets the sleep mode.
Abdollahi suggests a second related technique wherein a third latch is added to the two traditional latches comprising a conventional master-slave flip-flops, which are used globally throughout the VLSI circuit for signal throughput. The use of the third latch provides a means for forcing and restoring the state of the flip-flops during sleep mode operation. Besides adding the third latch, sleep control logic and multiplexer logic similar to the combinational logic must be included to accomplish the control. Hence, the second Abdollahi technique also imposes large area overhead, limiting the benefit for their stated purpose. More, the second technique may impose other global sleep mode complications in the ICs or IC processors within which they would be implemented.
Abdollahi also suggest a scan chain approach, which uses a scan path design to shift the logical circuits or gates to a low leakage state. In its simplest form, the Abdollahi scan chain approach requires an additional memory equivalent in size with the scan chain to restore the values of the latch circuits to their operational state, resetting them from sleep mode. That is, by controlling only the master latch (L1) part of the flip-flop, Abdollahi suggest that it is possible to employ the scan path to set the latch circuit output to a low leakage state. Such an approach includes an area overhead for at least the memory, and may counteract any improvement in stemming current leakage that could be realized.
German Patent Application No. DE 920050016US1 to T. Gemmeke, commonly owned and incorporated by reference herein, suggests an IVC-based approach that includes modifying the feedback loop of a master slave flip-flop to allow asynchronous controllability of the slave. The approach is unique, and appears promising but for the fact that its implementation would require a modification of standard latch technology design. That is, implementing such an approach in an existing IC or processor design would require modifying flip-flop design globally, and would therefore be disruptive in the design's manufacturing process. Required redesign would be likely to negatively impact project scheduling when the modified flip-flops are incorporated into existing designs. Moreover, the new proposed flip-flops would be inherently slower because of the third latch, so that overall timing during normal operational mode would be adversely affected, further complicating redesign efforts.
What would be desirable, therefore, in the field of VLSI circuit design and manufacture, is an improved IVC-based design and operation, which does not result in timing degradation in critical IC pathways, particularly for microprocessors, but realizes lowered global power dissipation throughout the IC or IC processor. The benefits should also minimize additional logic circuits and area overhead should realize lower power consumption during sleep mode operation that is, during set and reset, and should not affect conventional design and manufacturing flow.